Byron Theobald

AVA - Ai Vector Accelerator

The first semester of my Master’s involved a large group design project, our task was to create a hardware accelerator for AI tasks targeting the low-power CV32E40P RISC-V core designed by the OpenHW group.

The design implememented a minimal subset of the RISC-V ‘V’ Vector specification and acheived a 5x speed-up in TinyMLPerf compared to a non-vectorised runtime.


Me

From Suffolk, currently living in Hampshire.
Electrical and Electronic Engineer.
A keen cyclist, runner, hiker and photographer.